1. Field of the Invention
The present invention relates generally to a system and method of utilizing semaphores to synchronize multiple processes, and more particularly to a system and method for providing a semaphore bypass mechanism which reduces the amount of memory bandwidth waste.
2. Discussion of Related Art
One of the major requirements of a shared-memory multiprocessor is being able to coordinate processes that are working on a common task. Typically, a programmer will use semaphores to synchronize the processes. As such, semaphores are widely used to prevent asynchronous accesses to resources such as devices or memory locations. A common semaphore implementation is by means of a test and set mechanism. In such a mechanism, a semaphore is a flag or label which is stored in an addressable memory location for controlling access to certain regions of memory or other addressable resources.
When a process wishes to access a region of memory, for example memory region xyz, with which a semaphore is associated, and wants to prevent other processes from accessing that region, the process writes all 1's into the semaphore associated with that particular memory region. If a different process should wish to access memory region xyz, it first checks the semaphore and if it finds that there are all 1's in the semaphore, the process knows that it is denied access.
Heretofore, the second process continually goes to memory and checks the semaphore to see if memory region xyz is available. This constant checking of the semaphore is called "spin-locking" and it wastes an enormous amount of memory bandwidth since the semaphore may not be available for a long time and each semaphore access means a memory transaction. For a more in-depth discussion on the above discussed synchronization mechanism, see Hennessy, et al., Computer Architecture a Quantitative Approach, Chapter 8, Morgan Kaufman Publishers (1990) which is hereby incorporated by reference herein in its entirety.
U.S. Pat. No. 5,050,072 to Earnshaw et al. (hereinafter the Earnshaw patent) describes a system for reducing common bus contention. It allows the semaphore test bit and set operations to be performed on each CPU's local bus. An identical copy of the semaphore lock bits are stored locally in SRAM on each CPU. SRAM's have a limited amount of storage space, and eventually the SRAM memory is filled with semaphores and the mechanism described in the Earnshaw patent will once again fall victim to spin locking. In addition, the Earnshaw patent caches semaphores. Caching of semaphores is expensive and difficult, and decreases system performance. Specifically, the SRAM used in the Earnshaw patent stores the identical semaphore lock bits of every other CPU's SRAM, which wastes a great amount of space.